Hare: a Hierarchical Allocator for Registers in Multiple Issue Architectures

نویسندگان

  • David A. Berson
  • Rajiv Gupta
  • Mary Lou
چکیده

In this paper we present HARE, a new hierarchical approach to register allocation and assignment for multiple issue load/store architectures. HARE makes extensive use of execution estimates and functional unit availability information to select values for spilling and to place the spill code in locations that minimize the increase in the overall execution time of the program. Incorporated in HARE is recursive allocation, a new hierarchical allocation technique that compares the costs of spilling registers in a code region with reducing the number of registers used in subregions by spilling additional values. HARE also makes improvements in the register allocation techniques of coalescing, rematerialization, and register copy instructions.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Register Bank Assignment for Spatially Partitioned Processors

Demand for instruction level parallelism calls for increasing register bandwidth without increasing the number of register ports. Emerging architectures address this need by partitioning registers into multiple distributed banks, which offers a technology scalable substrate but a challenging compilation target. This paper introduces a register allocator for spatially partitioned architectures. ...

متن کامل

Register Allocation over the Program Dependence Graph Cindy

This paper describes RAP, a Register Allocator that allocates registers over the Program Dependence Graph (PDG) representation of a program in a hierarchical manner. The PDG program representation has been used successfully for scalar optimizations, the detection and improvement of parallelism for vector machines, multiple processor machines, and machines that exhibit instruction level parallel...

متن کامل

Coloring Register Pairs 1

Many architectures require that a program use pairs of adjacent registers to hold double-precision oating-point values. Register allocators based on Chaitin's graph-coloring technique have trouble with programs that contain both single-register values and values that require adjacent pairs of registers. In particular, Chaitin's algorithm often produces excessive spilling on such programs. This ...

متن کامل

A Method for Register Allocation to Loops in Multiple Register File Architectures

Multiple instruction issue processors place high demands on register le bandwidth. One solution to reduce this bottleneck is the use of multiple register les. Register allocation for these architectures then becomes exceedingly important as spill code increases memory bandwidth demands and decreases performance, especially within loops. Previously, we have addressed the issue of nding an optima...

متن کامل

Graph-Coloring Register Allocation for Irregular Architectures

The graph-coloring metaphor leads to elegant algorithms for register allocation that have been shown to be quite effective for regular architectures with plenty of registers. Published attempts to make these algorithms applicable to architectures that are irregular in their use of registers have yielded several incompatible extensions that handle only a small subset of the irregularities seen i...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1995